1. Field of Invention
The present invention relates to a gate array or an ASIC (Applied Specific IC or Structured Application Specific IC) or other semiconductor integrated circuit having a regular layout.
2. Description of the Related Art
A gate array type semiconductor integrated circuit uses a mask for patterning of the interconnects, so it is necessary prepare different masks for individual circuit designs. For this reason, further, a new mask must be provided whenever a circuit is corrected or changed.
On the other hand, in a so-called field programmable gate array (FPGA) type of semiconductor integrated circuit enabling programming of the logical functions, already laid out interconnects are selected by transistor switches to configure the desired circuit. For this reason, an FPGA has the advantage that the circuit configuration can be flexibly changed. However, there is the problem that the presence of transistor switches in the interconnect routes results in a large signal delay and a slower operation speed in comparison with a gate array. Further, since transistor switches must be used for connecting perpendicular interconnects, if the number of transistors is insufficient, the available interconnect resources become small and it becomes difficult to configure the desired circuit. In order to prevent such circumstances, many switch transistors must be provided, so there arises the problem of enlargement of the circuit area.
In recent years, a structured ASIC type of semiconductor integrated circuit enabling higher speed operation than an FPGA and, at the same time, able to be changed in circuit configuration more flexibly than a gate array has appeared.
In a structured ASIC, circuit cells having structures larger in size than the basic gates of a NAND circuit are used as the smallest units of the circuit. A circuit having the desired function is configured by mask routing for customizing part of the interconnects in accordance with the application unlike the FPGA explained above. The reconfigurable interconnect structure in an FPGA is very wasteful. If replacing this by mask routing, a circuit with greater waste than with a gate array, but much less waste than an FPGA can be developed in a short period.
As related art regarding the interconnect structure of a structured ASIC, for example, there is U.S. Pat. No. 6,476,493. The semiconductor device disclosed in U.S. Pat. No. 6,476,493 has first, second, and third metal layers. Each metal layer is formed with a plurality of parallel interconnects (strips). The interconnects of a certain metal layer are formed extending in a direction perpendicular to the interconnects of the metal layer just above or just beneath that metal layer. By the arrangement of the plurality of these interconnects side by side, a band structure is formed. Vias connecting these interconnects to each other and custom interconnects formed in the metal layers are used to form the desired interconnect pattern.
FIG. 17 is a first view of an example of an interconnect structure used in a structured ASIC. In the interconnect structure shown in FIG. 17, a plurality of parallel interconnects each having a constant length are formed in an a-th layer (a indicates any natural number) and an (a+1)-th layer above this layer. The interconnects of the a-th layer and the (a+1)-th layer are formed extending in directions perpendicular to each other. These plurality of parallel interconnects are arranged side by side in a direction vertical to the direction in which interconnects extend. A single band structure is formed by this array. Regular interconnect structures are formed in the a-th layer and the (a+1)-th layer by a repetition of the above band structure. Circuit cells are arrayed in a matrix along these band structures. The connections between circuit cells are customized by vias formed between the layers and jumper interconnects formed in an (a+2)-th layer.
In the interconnect structure shown in FIG. 17, to connect circuit cells, two vias and a jumper interconnect of the (a+2)-th layer are necessary as illustrated. Namely, a signal cannot be transmitted between circuit cells unless the signal passes through at least two vias. In general, the resistance value of a via is high; therefore, when the number of vias inserted in a signal route increases, there arises the disadvantage that the signal delay becomes large.
Further, in the interconnect structure shown in FIG. 17, two vias are needed in order to connect circuit cells; therefore, two interconnects become necessary for forming these vias. For example, when connecting two laterally arranged circuit cells, the two vertical interconnects at the boundary part of two circuit cells are used for forming the vias. The interconnect originally used for transmitting the signal in the vertical direction is used only for transferring the signal to the lateral direction; therefore, there is a problem of wasteful consumption of interconnect resource.
FIG. 18 is a second view of an example of an interconnect structure used in a structured ASIC. The interconnect structure shown in FIG. 18 is substantially the same as the interconnect structure shown in FIG. 17 concerning the a-th layer and the (a+1)-th layer. The interconnect structure shown in FIG. 18 is different from the interconnect structure shown in FIG. 17 in the point that a larger number of custom interconnects are formed in the (a+2)-th layer.
According to the interconnect structure shown in FIG. 18, a custom interconnect of the (a+2)-th layer is positively used for connecting circuit cells; therefore, there is the advantage that the interconnect resources of the a-th layer and the (a+1)-th layer can be saved. However, there is a possibility of the problem of a shortage arising in the interconnect resources of the (a+2)-th layer along with the increase of the interconnects of the (a+2)-th layer. Further, when forming the custom interconnects of the (a+2)-th layer by an electron beam (EB) system, etc., there arises the problem that the larger the amount of interconnects, the longer the processing time of the patterning.
FIG. 19 is a third view of an example of an interconnect structure used in a structured ASIC. The interconnect structure shown in FIG. 19 uses only vias for customizing the interconnects. The jumper interconnect of the (a+2)-th layer used for connecting circuit cells in the interconnect structure shown in FIG. 17 is replaced by jumper interconnects previously formed in the a-th layer and the (a+1)-th layer in the interconnect structure shown in FIG. 19. The state of connection between circuit cells is determined according to whether or not vias are formed in these jumpter interconnects.
According to the interconnect structure shown in FIG. 19, when correction of the circuit becomes necessary, only the mask of the vias formed between the a-th layer and the (a+1)-th layer need be redone, therefore, the cost required for the correction may be kept small. However, the point that two vias are necessary for connection between circuit cells is the same as that of the interconnect structure shown in FIG. 17, so an increase of the signal delay cannot be avoided. Further, the jumper interconnects are newly added to the a-th layer and the (a+1)-th layer; therefore, two interconnects in the vertical direction and two in the horizontal direction, which could be used in the interconnect structure shown in FIG. 17, become unusable for each circuit cell. Namely, as indicated by the dotted line arrows in FIG. 19, wasteful unusable interconnect tracks are formed, so there is the problem of reduction of the interconnect resources.